1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device which can be measured while correcting signal propagation delay time in a wire on a test jig interposing between a semiconductor tester and the semiconductor device and a timing error between propagation delay time in wires.
2. Description of the Background Art
In the case of measuring electric characteristics and the like of a semiconductor device by a semiconductor tester (hereinbelow, called a tester), usually, a jig for interface (hereinbelow, called a test jig) is interposed to electrically connect the tester and the semiconductor device. Since the tester is a large and expensive facility, it is commonly used for a plurality of kinds of semiconductor devices in a semiconductor device manufacturing factory. The number of terminals and the shape of a package vary according to semiconductor devices. By replacing a test jig with another, different kinds of semiconductor devices can be measured by the same tester.
FIG. 14 is a diagram for explaining the test jig.
Referring to FIG. 14, a tester 200 has drivers 204a to 204x for outputting waveforms to a plurality of connection terminals, and comparators 206a to 206x for measuring waveforms of the terminals.
A test jig 202 includes a socket 212 for attaching a semiconductor device and transmission lines 208a to 208x for connecting a plurality of terminals of the socket 212 to the different connection terminals of the tester 200. As the transmission lines 208a to 208x, for example, coaxial lines 210 are used.
FIG. 15 is a diagram showing a state where a semiconductor device is attached to the socket of the test jig.
Referring to FIG. 15, when the semiconductor device is attached to the socket 212, the transmission lines 208a to 208x are electrically connected to terminals of the semiconductor device.
For example, in the case of measuring time (such as access time) between receipt of a signal from the tester and outputting of any signal by the semiconductor device, it is known that the excess time has to be subtracted from the time measured as access time. The excess time is obtained by adding the time required for a signal outputted from the tester 200 to reach the semiconductor device via the transmission lines 208a to 208x on the test jig 202 and the time required for the signal outputted from the semiconductor device to reach the tester 200 via the signal transmission lines 208a to 208x. 
That is, the delay time caused by the signal transmission lines 208a to 208x existing on the test jig 202 has to be especially considered and excluded. Usually, coaxial cables or wiring patterns formed on a printed wiring board are used as the transmission lines 208a to 208x. Due to the wiring length, generally, signal propagation delay time of the order of a few ns occurs.
Conventionally, a method called TDR (Time Domain Reflectmetry) which preliminarily measures the signal propagation delay time on the test jig by a tester is used. Then, another method of subtracting the preliminarily measured propagation delay time at the time of measuring electric characteristics of a semiconductor device is used.
FIG. 16 is a diagram for explaining measurement of propagation delay time by the TDR method.
FIG. 17 is a waveform chart at the time of measuring the propagation delay time by the TDR method.
Referring to FIGS. 16 and 17, in order to measure time T_cable of propagation of a signal through the transmission line 208a, a signal wave is outputted from the driver 204a of the tester in a state where the semiconductor device is not attached to the socket of the test jig, that is, an output end 214 of the transmission line 208a is open.
The signal wave outputted from the driver 204a passes through the transmission line 208. The signal wave is totally reflected by the output terminal 214 which is open. The signal wave passes through the transmission line 208a again, and is received by the comparator 206a of the tester. The total time is measured by the tester. The measured time is time required for the signal wave to go and return through the transmission line 208a and is twice as long as the propagation time T_cable. The time which is the half of the measured time is defined as propagation delay time in the transmission line 208a. 
FIG. 18 is a diagram showing the correspondence between the transmission lines on the test jig and propagation delay time.
Referring to FIG. 18, propagation delay time in the transmission lines 208a, 208b, 208c, . . . , 208x is set as T_cable-a, T_cable-b, T_cable-c, . . . , T_cable-x, respectively. Due to error factors such as variations in wiring length and mounting conditions (such as soldering) of the socket, the signal propagation delay time T_cable-a to T_cable-x in the transmission lines 208a to 208x extending from the tester to the socket varies.
FIG. 19 is a waveform chart showing a state where the waveform outputted from the tester propagates to the output end of each of the transmission lines.
Referring to FIG. 19, it is assumed that waveforms observed at the output ends of the transmission lines 208a to 208x are waveforms W208a to W208x, respectively. Propagation delay time in all the signal transmission lines 208a to 208x is measured in advance. At the time of measuring the electric characteristics of a semiconductor device or the like, measurement is performed by supplying a signal to the semiconductor device at a timing obtained by subtracting the measured propagation delay time T_cable-a to T_cable-x in the transmission lines 208a to 208x. 
In such a manner, although a timing error in the propagation time of Aa occurs at the ends of the socket before correction of the propagation delay time by the TDR method, the timing error can be shortened. The measured propagation delay time T_cable-a to T_cable-x is recorded as data for correction in the tester. The tester adjusts the timing of making the driver output data with reference to the correction data.
FIG. 20 is a waveform chart showing waveforms at the output ends after correction by the tester.
Referring to FIGS. 19 and 20, before correction of the propagation delay time by the TDR method, there is a timing error xcex94a in the propagation delay time between the transmission lines 208a to 208x at the ends of the socket. By performing the timing correction, the timing error xcex94a can be shortened to about xcex94b. Consequently, the correction can be made so that a semiconductor device can receive substantially (actually) simultaneously output signals at a timing, which are outputted from the tester.
In recent years, as the operating frequency increases, as seen in a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) or the like, there occurs a necessity to measure a semiconductor device which is requested to have a very small error between a data output timing reference signal and a data output timing.
The measuring accuracy has to be therefore further improved. As described above, in order to improve the accuracy of measuring a semiconductor device by a tester, it is necessary to measure the semiconductor device after accurately correcting the signal propagation delay time on the test jig, a timing error caused by variations in wiring length among the transmission lines, and the like.
Referring again to FIG. 16, in the method using the conventional TDR method, when the propagation delay time of, for example, the transmission line 208a is measured, since the timing accuracy of both the driver 204a and the comparator 206a is involved, the timing correction is limited. The timing error between the plurality of transmission lines (hereinbelow, called a skew among pins) is a value of, for example, about xc2x1several hundreds ps. A nominal value of the value is shown under the name such as a driver skew or the like in the tester.
In the case of a semiconductor device requiring a high accuracy timing condition (for example, an error of xc2x1100 ps or less) such as a DDR SDRAM described above, there is a problem such that measurement cannot be done due to the limitation of the timing correction.
An object of the invention is to provide a semiconductor device which can be measured while accurately correcting a timing error by a test jig.
In short, the invention relates to a semiconductor device having a reference terminal, a plurality of terminals, a capturing circuit, a data holding circuit, and an output circuit.
The reference terminal receives a reference signal. The capturing circuit captures an input signal supplied to the plurality of terminals in accordance with the reference signal and temporarily holds the input signal. The data holding circuit receives the data held by the capturing circuit and holds data of an amount corresponding to a predetermined number of capturing times. The output circuit outputs the data held by the data holding circuit to the outside.
According to another aspect of the invention, there is provided a semiconductor device testing method of testing a semiconductor device by a tester via a test jig, including the steps of: attaching a semiconductor device to the test jig; supplying the reference signal and the input signal from the tester and allowing the data holding circuit to hold delay amount data of each of a plurality of signal transmission lines of the test jig corresponding to the plurality of terminals; reading the delay amount data by the tester via the test jig; and correcting a timing of a signal which is outputted to the plurality of terminals by the tester in accordance with the delay amount data.
The semiconductor device includes: a reference terminal for receiving a reference terminal; a plurality of terminals; and a data holding circuit for holding data corresponding to a time difference between the reference signal and an input signal supplied to the plurality of terminals.
Consequently, a main advantage of the present invention is that, since the timing of the tester is corrected so as to be adapted to the test jig with high accuracy, even a semiconductor device having a strict specification of a skew between pins can be also measured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.